/* ------------------------------------------
 * Copyright (c) 2017, Synopsys, Inc. All rights reserved.

 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:

 * 1) Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.

 * 2) Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation and/or
 * other materials provided with the distribution.

 * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
 * be used to endorse or promote products derived from this software without
 * specific prior written permission.

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
   --------------------------------------------- */
#ifndef _CREG_HSDC_H_
#define _CREG_HSDC_H_

#include "creg_hsdc_reg.h"

#define MAX_DEBUG_MSG_FPGA    (128)

/* CREG bit definitions */
#define A_UPDATE              (0x00000001U)

typedef enum CREG_HSDC_VERSION {
	CREG_HSDC_VERSION_DAY = 0,
	CREG_HSDC_VERSION_MONTH,
	CREG_HSDC_VERSION_YEAR,
	CREG_HSDC_VERSION_MIN,
	CREG_HSDC_VERSION_HOUR,
	CREG_HSDC_VERSION_NONE
} CREG_HSDC_VERSION_T;

typedef enum CREG_HSDC_REVISION {
	CREG_HSDC_REVISION_R1_1 = 0,
	CREG_HSDC_REVISION_R1_2,
	CREG_HSDC_REVISION_R1_0,
	CREG_HSDC_REVISION_R1_3,
	CREG_HSDC_REVISION_None
} CREG_HSDC_REVISION_T;

typedef enum CREG_HSDC_MASTER {
	CREG_HSDC_MASTER_ARCHS38 = 0,
	CREG_HSDC_MASTER_RTT,
	CREG_HSDC_MASTER_AXITUNNEL,
	CREG_HSDC_MASTER_HDMI_V,
	CREG_HSDC_MASTER_HDMI_A,
	CREG_HSDC_MASTER_USB,
	CREG_HSDC_MASTER_ETHERNET,
	CREG_HSDC_MASTER_SDIO,
	CREG_HSDC_MASTER_GFX,
	CREG_HSDC_MASTER_DMAC1,
	CREG_HSDC_MASTER_DMAC2,
	CREG_HSDC_MASTER_DVFS,
	CREG_HSDC_MASTER_NONE
} CREG_HSDC_MASTER_T;

typedef enum CREG_HSDC_SLAVE {
	CREG_HSDC_SLAVE_NOSLAVE = 0,
	CREG_HSDC_SLAVE_DDR1,
	CREG_HSDC_SLAVE_SRAM,
	CREG_HSDC_SLAVE_AXITUNNEL,
	CREG_HSDC_SLAVE_EBI,
	CREG_HSDC_SLAVE_ROM,
	CREG_HSDC_SLAVE_AXI2APB,
	CREG_HSDC_SLAVE_DDR2,
	CREG_HSDC_SLAVE_DDR3,
	CREG_HSDC_SLAVE_HS38X4IOC,
	CREG_HSDC_SLAVE_HS38X4DMI,
	CREG_HSDC_SLAVE_NONE
} CREG_HSDC_SLAVE_T;

typedef enum CREG_HSDC_APERTURE {
	CREG_HSDC_APERTURE_0 = 0,       // 0x0000.0000 - 0x0FFF.FFFF
	CREG_HSDC_APERTURE_1,           // 0x1000.0000 - 0x1FFF.FFFF
	CREG_HSDC_APERTURE_2,           // 0x2000.0000 - 0x2FFF.FFFF
	CREG_HSDC_APERTURE_3,           // 0x3000.0000 - 0x3FFF.FFFF
	CREG_HSDC_APERTURE_4,           // 0x4000.0000 - 0x4FFF.FFFF
	CREG_HSDC_APERTURE_5,           // 0x5000.0000 - 0x5FFF.FFFF
	CREG_HSDC_APERTURE_6,           // 0x6000.0000 - 0x6FFF.FFFF
	CREG_HSDC_APERTURE_7,           // 0x7000.0000 - 0x7FFF.FFFF
	CREG_HSDC_APERTURE_8,           // 0x8000.0000 - 0x8FFF.FFFF
	CREG_HSDC_APERTURE_9,           // 0x9000.0000 - 0x9FFF.FFFF
	CREG_HSDC_APERTURE_10,          // 0xA000.0000 - 0xAFFF.FFFF
	CREG_HSDC_APERTURE_11,          // 0xB000.0000 - 0xBFFF.FFFF
	CREG_HSDC_APERTURE_12,          // 0xC000.0000 - 0xCFFF.FFFF
	CREG_HSDC_APERTURE_13,          // 0xD000.0000 - 0xDFFF.FFFF
	CREG_HSDC_APERTURE_14,          // 0xE000.0000 - 0xEFFF.FFFF
	CREG_HSDC_APERTURE_15,          // 0xF000.0000 - 0xFFFF.FFFF
	CREG_HSDC_APERTURE_NONE
} CREG_HSDC_APERTURE_T;

typedef enum CREG_HSDC_OFFSET {
	CREG_HSDC_OFFSET_0 = 0,         // 0x0000.0000 - 0x0FFF.FFFF
	CREG_HSDC_OFFSET_1,             // 0x1000.0000 - 0x1FFF.FFFF
	CREG_HSDC_OFFSET_2,             // 0x2000.0000 - 0x2FFF.FFFF
	CREG_HSDC_OFFSET_3,             // 0x3000.0000 - 0x3FFF.FFFF
	CREG_HSDC_OFFSET_4,             // 0x4000.0000 - 0x4FFF.FFFF
	CREG_HSDC_OFFSET_5,             // 0x5000.0000 - 0x5FFF.FFFF
	CREG_HSDC_OFFSET_6,             // 0x6000.0000 - 0x6FFF.FFFF
	CREG_HSDC_OFFSET_7,             // 0x7000.0000 - 0x7FFF.FFFF
	CREG_HSDC_OFFSET_8,             // 0x8000.0000 - 0x8FFF.FFFF
	CREG_HSDC_OFFSET_9,             // 0x9000.0000 - 0x9FFF.FFFF
	CREG_HSDC_OFFSET_10,            // 0xA000.0000 - 0xAFFF.FFFF
	CREG_HSDC_OFFSET_11,            // 0xB000.0000 - 0xBFFF.FFFF
	CREG_HSDC_OFFSET_12,            // 0xC000.0000 - 0xCFFF.FFFF
	CREG_HSDC_OFFSET_13,            // 0xD000.0000 - 0xDFFF.FFFF
	CREG_HSDC_OFFSET_14,            // 0xE000.0000 - 0xEFFF.FFFF
	CREG_HSDC_OFFSET_15,            // 0xF000.0000 - 0xFFFF.FFFF
	CREG_HSDC_OFFSET_NONE
} CREG_HSDC_OFFSET_T;

typedef struct CREG_HSDC_APERTURECONFIG {
	CREG_HSDC_MASTER_T mst;
	CREG_HSDC_SLAVE_T slv;
	CREG_HSDC_OFFSET_T offset;
	CREG_HSDC_APERTURE_T aperture;
	uint32_t intnum;
} CREG_HSDC_APERTURECONFIG_T;

typedef enum CREG_HSDC_INTSOURCE {
	CREG_HSDC_INTSOURCE_GPIO_A0 = 0,
	CREG_HSDC_INTSOURCE_GPIO_A1,
	CREG_HSDC_INTSOURCE_GPIO_A2,
	CREG_HSDC_INTSOURCE_GPIO_A3,
	CREG_HSDC_INTSOURCE_GPIO_A4,
	CREG_HSDC_INTSOURCE_GPIO_A5,
	CREG_HSDC_INTSOURCE_GPIO_A6,
	CREG_HSDC_INTSOURCE_GPIO_A7,
	CREG_HSDC_INTSOURCE_GPIO_A8,
	CREG_HSDC_INTSOURCE_GPIO_A9,
	CREG_HSDC_INTSOURCE_GPIO_A10,
	CREG_HSDC_INTSOURCE_GPIO_A11,
	CREG_HSDC_INTSOURCE_GPIO_A12,
	CREG_HSDC_INTSOURCE_GPIO_A13,
	CREG_HSDC_INTSOURCE_GPIO_A14,
	CREG_HSDC_INTSOURCE_GPIO_A15,
	CREG_HSDC_INTSOURCE_GPIO_A16,
	CREG_HSDC_INTSOURCE_GPIO_A17,
	CREG_HSDC_INTSOURCE_GPIO_A18,
	CREG_HSDC_INTSOURCE_GPIO_A19,
	CREG_HSDC_INTSOURCE_GPIO_A20,
	CREG_HSDC_INTSOURCE_GPIO_A21,
	CREG_HSDC_INTSOURCE_GPIO_A22,
	CREG_HSDC_INTSOURCE_GPIO_A23,
	CREG_HSDC_INTSOURCE_GPIO_A24,
	CREG_HSDC_INTSOURCE_GPIO_A25,
	CREG_HSDC_INTSOURCE_GPIO_A26,
	CREG_HSDC_INTSOURCE_GPIO_A27,
	CREG_HSDC_INTSOURCE_GPIO_A28,
	CREG_HSDC_INTSOURCE_GPIO_A29,
	CREG_HSDC_INTSOURCE_GPIO_A30,
	CREG_HSDC_INTSOURCE_GPIO_A31,
	CREG_HSDC_INTSOURCE_NONE
} CREG_HSDC_INTSOURCE_T;

typedef enum CREG_HSDC_TUNNELPRIORITY {
	CREG_HSDC_TUNNELPRIORITY_EQUAL = 0,
	CREG_HSDC_TUNNELPRIORITY_MASTER,
	CREG_HSDC_TUNNELPRIORITY_SLAVE,
	CREG_HSDC_TUNNELPRIORITY_NONE
} CREG_HSDC_TUNNELPRIORITY_T;

typedef enum CREG_HSDC_TUNNELPDMODE {
	CREG_HSDC_TUNNELPDMODE_NORMAL=0,
	CREG_HSDC_TUNNELPDMODE_POWERDOWN,
	CREG_HSDC_TUNNELPDMODE_NONE
} CREG_HSDC_TUNNELPDMODE_T;

typedef enum CREG_HSDC_TUNNELIOMODE {
	CREG_HSDC_TUNNELIOMODE_SSTL=0,
	CREG_HSDC_TUNNELIOMODE_LVCMOS,
	CREG_HSDC_TUNNELIOMODE_NONE
} CREG_HSDC_TUNNELIOMODE_T;

typedef enum CREG_HSDC_STARTMODE {
	CREG_HSDC_STARTMODE_MANUAL = 0,
	CREG_HSDC_STARTMODE_AUTO,
	CREG_HSDC_STARTMODE_NONE
} CREG_HSDC_STARTMODE_T;

typedef enum CREG_HSDC_POLARITY {
	CREG_HSDC_POLARITY_LOW = 0,
	CREG_HSDC_POLARITY_HIGH,
	CREG_HSDC_POLARITY_NONE
} CREG_HSDC_POLARITY_T;

typedef enum CREG_HSDC_MULTICOREMODE {
	CREG_HSDC_MULTICOREMODE_SINGLE = 0,
	CREG_HSDC_MULTICOREMODE_DUAL,
	CREG_HSDC_MULTICOREMODE_TRIPLE,
	CREG_HSDC_MULTICOREMODE_QUAD,
	CREG_HSDC_MULTICOREMODE_NONE,
} CREG_HSDC_MULTICOREMODE_T;

typedef enum CREG_HSDC_CORE {
	CREG_HSDC_CORE_ARCHS38X4_1 = 0,
	CREG_HSDC_CORE_ARCHS38X4_2,
	CREG_HSDC_CORE_ARCHS38X4_3,
	CREG_HSDC_CORE_ARCHS38X4_4,
	CREG_HSDC_CORE_NONE
} CREG_HSDC_CORE_T;

typedef enum CREG_HSDC_DEBUGUARTMODE {
	CREG_HSDC_DEBUGUARTMODE_NORMAL = 0,
	CREG_HSDC_DEBUGUARTMODE_DEBUG,
	CREG_HSDC_DEBUGUARTMODE_NONE
} CREG_HSDC_DEBUGUARTMODE_T;

typedef enum CREG_HSDC_DDRHOSTPORT {
	CREG_HSDC_DDRHOSTPORT_0 = 0,
	CREG_HSDC_DDRHOSTPORT_1,
	CREG_HSDC_DDRHOSTPORT_2,
	CREG_HSDC_DDRHOSTPORT_3,
	CREG_HSDC_DDRHOSTPORT_NONE
} CREG_HSDC_DDRHOSTPORT_T;

// Number of SPI-IP's
typedef enum CREG_HSDC_SPISEL {
	CREG_HSDC_SPISEL_0 = 0,
	CREG_HSDC_SPISEL_1,
	CREG_HSDC_SPISEL_2,
	CREG_HSDC_SPISEL_NONE
} CREG_HSDC_SPISEL_T;

// Number of CS each SPI-IP
// Remark: only SPI0 has 4x CS lines, SPI1 and SPI2 have 3x CS lines
typedef enum CREG_HSDC_SPICSSEL {
	CREG_HSDC_SPICSSEL_0 = 0,
	CREG_HSDC_SPICSSEL_1,
	CREG_HSDC_SPICSSEL_2,
	CREG_HSDC_SPICSSEL_3,
	CREG_HSDC_SPICSSEL_NONE
} CREG_HSDC_SPICSSEL_T;

typedef enum CREG_HSDC_SPICSCTRL {
	CREG_HSDC_SPICSCTRL_CSBYSPI             = 0,
	CREG_HSDC_SPICSCTRL_CSBYCREGVALUE0      = 2,
	CREG_HSDC_SPICSCTRL_CSBYCREGVALUE1,
	CREG_HSDC_SPICSCTRL_NONE
} CREG_HSDC_SPICSCTRL_T;

typedef enum CREG_HSDC_I2SCLKCTRL {
	CREG_HSDC_I2SCLKCTRL_SEPARATE = 0,
	CREG_HSDC_I2SCLKCTRL_SHARED,
	CREG_HSDC_I2SCLKCTRL_NONE
} CREG_HSDC_I2SCLKCTRL_T;

typedef enum CREG_HSDC_GPIOSEL {
	CREG_HSDC_GPIOSEL_0 = 0,
	CREG_HSDC_GPIOSEL_1,
	CREG_HSDC_GPIOSEL_2,
	CREG_HSDC_GPIOSEL_3,
	CREG_HSDC_GPIOSEL_4,
	CREG_HSDC_GPIOSEL_5,
	CREG_HSDC_GPIOSEL_6,
	CREG_HSDC_GPIOSEL_7,
	CREG_HSDC_GPIOSEL_NONE
} CREG_HSDC_GPIOSEL_T;

typedef enum CREG_HSDC_GPIO {
	CREG_HSDC_GPIOMUX_GPIO = 0,   // GPIO TO OUTPUT PINS
	CREG_HSDC_GPIOMUX_UART,
	CREG_HSDC_GPIOMUX_SPI,
	CREG_HSDC_GPIOMUX_I2C,
	CREG_HSDC_GPIOMUX_PWM_4,        // GPIO AND/OR PWM
	CREG_HSDC_GPIOMUX_PWM_5,        // GPIO AND/OR PWM
	CREG_HSDC_GPIOMUX_PWM_6,        // GPIO AND/OR PWM
	CREG_HSDC_GPIOMUX_PWM_7,        // GPIO AND/OR PWM
	CREG_HSDC_GPIOMUX_NONE
} CREG_HSDC_GPIOMUX_T;

typedef enum CREG_HSDC_DBGSEL {
	CREG_HSDC_DBGSEL_0 = 0,
	CREG_HSDC_DBGSEL_1,
	CREG_HSDC_DBGSEL_2,
	CREG_HSDC_DBGSEL_3,
	CREG_HSDC_DBGSEL_4,
	CREG_HSDC_DBGSEL_5,
	CREG_HSDC_DBGSEL_NONE
} CREG_HSDC_DBGSEL_T;

typedef enum CREG_HSDC_DBG {
	CREG_HSDC_DBGMUX_GPIO = 0,    // GPIO TO OUTPUT PINS
	CREG_HSDC_DBGMUX_OTHER,
	CREG_HSDC_DBGMUX_NONE
} CREG_HSDC_DBGMUX_T;

typedef enum CREG_HSDC_DMAFCSEL {
	CREG_HSDC_DMAFCSEL_0,
	CREG_HSDC_DMAFCSEL_1,
	CREG_HSDC_DMAFCSEL_2,
	CREG_HSDC_DMAFCSEL_NONE
} CREG_HSDC_DMAFCSEL_T;

typedef enum CREG_HSDC_DMAMUX {
	CREG_HSDC_DMAMUX_SPI0 = 0,
	CREG_HSDC_DMAMUX_SPI1,
	CREG_HSDC_DMAMUX_SPI2,
	CREG_HSDC_DMAMUX_I2C0,
	CREG_HSDC_DMAMUX_I2C1,
	CREG_HSDC_DMAMUX_I2C2,
	CREG_HSDC_DMAMUX_UART0,
	CREG_HSDC_DMAMUX_UART1,
	CREG_HSDC_DMAMUX_UART2,
	CREG_HSDC_DMAMUX_NONE
} CREG_HSDC_DMAMUX_T;

typedef enum CREG_HSDC_ARCCLKDIV {
	CREG_HSDC_ARCCLKDIV_DIV1 = 0,
	CREG_HSDC_ARCCLKDIV_DIV2,
	CREG_HSDC_ARCCLKDIV_NONE
} CREG_HSDC_ARCCLKDIV_T;

typedef struct CREG_HSDC_START_T {
	uint8_t start;
	CREG_HSDC_STARTMODE_T start_mode;
	CREG_HSDC_POLARITY_T polarity;
	CREG_HSDC_MULTICOREMODE_T multicoremode;
} CREG_HSDC_START_T;

typedef enum CREG_HSDC_DDRCTRL {
	CREG_HSDC_DDRCTRL_UMCTL = 0,
	CREG_HSDC_DDRCTRL_PHY,
	CREG_HSDC_DDRCTRL_NONE
} CREG_HSDC_DDRCTRL_T;

// Boot register
typedef enum CREG_HSDC_BOOTMIRROR {
	CREG_HSDC_BOOTMIRROR_DISABLED = 0,
	CREG_HSDC_BOOTMIRROR_INTERNALROM,
	CREG_HSDC_BOOTMIRROR_EXTERNALROM,
	CREG_HSDC_BOOTMIRROR_EXTERNALROMTUNNEL,
	CREG_HSDC_BOOTMIRROR_NONE
} CREG_HSDC_BOOTMIRROR_T;

typedef enum CREG_HSDC_IMAGELOCATION {
	CREG_HSDC_IMAGELOCATION_BYPASS = 0,
	CREG_HSDC_IMAGELOCATION_SPIFLASH,
	CREG_HSDC_IMAGELOCATION_EBI,
	CREG_HSDC_IMAGELOCATION_TUNNEL,
	CREG_HSDC_IMAGELOCATION_NONE
} CREG_HSDC_IMAGELOCATION_T;

typedef enum CREG_HSDC_AUX {
	CREG_HSDC_AUX_DDR_SG125_4GB_X8_1RANK = 0,
	CREG_HSDC_AUX_DDR_SG125_4GB_X8_2RANK,
	CREG_HSDC_AUX_DDR_SG125_4GB_X16_1RANK,
	CREG_HSDC_AUX_DDR_SG125_4GB_X16_2RANK,
	CREG_HSDC_AUX_DDR_SG125_8GB_X8_1RANK,
	CREG_HSDC_AUX_DDR_SG125_8GB_X8_2RANK_ILLEGAL,
	CREG_HSDC_AUX_DDR_SG125_8GB_X16_1RANK,
	CREG_HSDC_AUX_DDR_SG125_8GB_X16_2RANK,
	CREG_HSDC_AUX_DDR_SG15E_4GB_X8_1RANK,
	CREG_HSDC_AUX_DDR_SG15E_4GB_X8_2RANK,
	CREG_HSDC_AUX_DDR_SG15E_4GB_X16_1RANK,
	CREG_HSDC_AUX_DDR_SG15E_4GB_X16_2RANK,
	CREG_HSDC_AUX_DDR_SG15E_8GB_X8_1RANK,
	CREG_HSDC_AUX_DDR_SG15E_8GB_X8_2RANK_ILLEGAL,
	CREG_HSDC_AUX_DDR_SG15E_8GB_X16_1RANK,
	CREG_HSDC_AUX_DDR_SG15E_8GB_X16_2RANK,
	CREG_HSDC_AUX_DDR_FPGA_MCTL,
	CREG_HSDC_AUX_DDR_FPGA_PUBM,
	CREG_HSDC_AUX_NONE
} CREG_HSDC_AUX_T;

extern void creg_hsdc_init_device(CREG_HSDC_STRUCT_PTR creg_regs);

extern uint32_t creg_hsdc_get_version(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_VERSION_T v);

extern void creg_hsdc_get_revision(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_REVISION_T *revision);

extern void creg_hsdc_set_slave(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_MASTER_T mst, CREG_HSDC_SLAVE_T slv, CREG_HSDC_APERTURE_T ap);

extern void creg_hsdc_get_slave(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_MASTER_T mst, CREG_HSDC_SLAVE_T *slv, CREG_HSDC_APERTURE_T ap);

extern void creg_hsdc_set_offset(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_MASTER_T mst, CREG_HSDC_OFFSET_T offset, CREG_HSDC_APERTURE_T ap);

extern void creg_hsdc_get_offset(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_MASTER_T mst, CREG_HSDC_OFFSET_T *offset, CREG_HSDC_APERTURE_T ap);

extern void creg_hsdc_update(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_MASTER_T mst);

extern void creg_hsdc_setpae(CREG_HSDC_STRUCT_PTR creg_regs, uint32_t pae);

extern void creg_hsdc_update_pae(CREG_HSDC_STRUCT_PTR creg_regs);

// return 0 when programming aperture ok
extern int32_t creg_hsdc_program_aperture(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_APERTURECONFIG_T *config);

// interrupt functions
extern void creg_hsdc_clr_ena_irq(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_CORE_T core);

extern void creg_hsdc_set_ena_irq(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_CORE_T core);

extern void creg_hsdc_set_sts_irq(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_CORE_T core);

extern uint32_t creg_hsdc_get_sts_irq(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_CORE_T core);

extern void creg_hsdc_clr_sts_irq(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_CORE_T core);

extern uint32_t creg_hsdc_get_tunnel_sts(CREG_HSDC_STRUCT_PTR creg_regs);

extern void creg_hsdc_set_tunnel_priority(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_TUNNELPRIORITY_T pr);

extern void creg_hsdc_set_tunnel_io_mode(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_TUNNELIOMODE_T pd);

extern void creg_hsdc_set_tunnel_pd_mode(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_TUNNELPDMODE_T pd);

extern void creg_hsdc_set_ddr_latency(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_DDRHOSTPORT_T port, uint8_t latency);

extern void creg_hsdc_set_sram_latency(CREG_HSDC_STRUCT_PTR creg_regs, uint8_t latency);

extern void creg_hsdc_set_spi_cs_ctrl(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_SPISEL_T sel, CREG_HSDC_SPICSSEL_T cs, CREG_HSDC_SPICSCTRL_T ctrl);

extern void creg_hsdc_set_i2s_clk_ctrl(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_I2SCLKCTRL_T sel);

extern void creg_hsdc_set_gpio_mux(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_GPIOSEL_T sel, CREG_HSDC_GPIOMUX_T mux);

extern void creg_hsdc_set_dbg_mux(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_DBGSEL_T sel, CREG_HSDC_DBGMUX_T mux);

extern void creg_hsdc_set_dma_mux(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_DMAFCSEL_T sel, CREG_HSDC_DMAMUX_T mux);

extern void creg_hsdc_set_arc_clk_div(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_ARCCLKDIV_T div);

extern CREG_HSDC_ARCCLKDIV_T creg_hsdc_get_arc_clk_div(CREG_HSDC_STRUCT_PTR creg_regs);

// Arc start
extern void creg_hsdc_start_core(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_START_T *start);

// Arc start special for Wdt
extern void creg_hsdc_set_start_mode(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_STARTMODE_T mode);

extern void creg_hsdc_get_debug_uart_mode(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_DEBUGUARTMODE_T *mode);

extern void creg_hsdc_get_multi_core_mode(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_MULTICOREMODE_T *mode);

// Ddr
extern void creg_hsdc_set_ddr_enable(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_DDRCTRL_T ctrl, uint32_t enable);

extern void creg_hsdc_wait_ddr_init_done(CREG_HSDC_STRUCT_PTR creg_regs);

// Boot
extern void creg_hsdc_get_boot_mirror(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_BOOTMIRROR_T *mirror);

extern void creg_hsdc_set_boot_mirror(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_BOOTMIRROR_T mirror);

extern void creg_hsdc_get_image_location(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_IMAGELOCATION_T *location);

extern void creg_hsdc_get_aux(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_AUX_T *aux);

extern void creg_hsdc_set_aux(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_AUX_T aux);

extern void creg_hsdc_sw_reset(CREG_HSDC_STRUCT_PTR creg_regs);

extern void creg_hsdc_set_kernel_entrypoint(CREG_HSDC_STRUCT_PTR creg_regs, CREG_HSDC_CORE_T core, uint32_t address);

#endif /*  _CREG_HSDC_H_ */
